Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
date_generatedWed Aug 7 16:49:46 2013 product_versionVivado v2013.2
build_version272601 os_platformLIN32
registration_id210701084_1777489062_0_015 tool_flowVivado
betaFALSE route_designTRUE
target_familyzynq target_devicexc7z020
target_packageclg484 target_speed-1
random_id076321c06bd65023ab135545b3942b69 project_idfc0b88d8fac04eefbb63ad5686f5c712
project_iteration2

user_environment
os_nameUbuntu os_releaseUbuntu 13.04
cpu_nameIntel(R) Core(TM) i5 CPU M 560 @ 2.67GHz cpu_speed2660.039 MHz
total_processors2 system_ram0.000 GB

vivado_usage
project_data
srcsetcount=2 constraintsetcount=1 designmode=RTL prproject=false
reconfigpartitioncount=0 reconfigmodulecount=0 hdproject=false partitioncount=0
synthesisstrategy=Vivado Synthesis Defaults implstrategy=Vivado Implementation Defaults currentsynthesisrun=synth_1 currentimplrun=impl_1
totalsynthesisruns=1 totalimplruns=1 board=ZedBoard Zynq Evaluation and Development Kit
other_data
guimode=1

unisim_transformation
pre_unisim_transformation
bibuf=130 bufg=1 carry4=20 fdre=1685
fdse=66 gnd=8 ibuf=8 lut1=133
lut2=48 lut3=145 lut4=806 lut5=1213
lut6=1270 muxf7=160 obuf=8 ps7=1
srl16e=23 srlc32e=47 vcc=6
post_unisim_transformation
bibuf=130 bufg=1 carry4=20 fdre=1685
fdse=66 gnd=8 ibuf=8 lut1=133
lut2=48 lut3=145 lut4=806 lut5=1213
lut6=1270 muxf7=160 obuf=8 ps7=1
srl16e=23 srlc32e=47 vcc=6

ip_statistics
IP_Integrator/1
iptotal=1 x_ipvendor=xilinx.com x_iplanguage=VHDL
axi_protocol_converter_v2_0_axi_protocol_converter/1
iptotal=1 x_ipproduct=Vivado 2013.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_protocol_converter x_ipversion=2.0 x_ipcorerevision=1 x_iplanguage=VHDL
c_family=zynq c_m_axi_protocol=2 c_s_axi_protocol=1 c_ignore_id=0
c_axi_id_width=12 c_axi_addr_width=32 c_axi_data_width=32 c_axi_supports_write=1
c_axi_supports_read=1 c_axi_supports_user_signals=0 c_axi_awuser_width=1 c_axi_aruser_width=1
c_axi_wuser_width=1 c_axi_ruser_width=1 c_axi_buser_width=1 c_translation_mode=2
proc_sys_reset/1
iptotal=1 x_ipproduct=Vivado 2013.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=proc_sys_reset x_ipversion=5.0 x_ipcorerevision=1 x_iplanguage=VHDL
c_family=zynq c_ext_rst_width=4 c_aux_rst_width=4 c_ext_reset_high=0
c_aux_reset_high=0 c_num_bus_rst=1 c_num_perp_rst=1 c_num_interconnect_aresetn=1
c_num_perp_aresetn=1
processing_system7/1
iptotal=1 x_ipproduct=Vivado 2013.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=processing_system7 x_ipversion=5.2 x_ipcorerevision=0 x_iplanguage=VHDL
c_en_emio_enet0=0 c_en_emio_enet1=0 c_en_emio_trace=0 c_include_trace_buffer=0
c_trace_buffer_fifo_size=128 use_trace_data_edge_detector=0 c_trace_buffer_clock_delay=12 c_emio_gpio_width=64
c_include_acp_trans_check=0 c_use_default_acp_user_val=0 c_s_axi_acp_aruser_val=31 c_s_axi_acp_awuser_val=31
c_m_axi_gp0_id_width=12 c_m_axi_gp0_enable_static_remap=0 c_m_axi_gp1_id_width=12 c_m_axi_gp1_enable_static_remap=0
c_s_axi_gp0_id_width=6 c_s_axi_gp1_id_width=6 c_s_axi_acp_id_width=3 c_s_axi_hp0_id_width=6
c_s_axi_hp0_data_width=64 c_s_axi_hp1_id_width=6 c_s_axi_hp1_data_width=64 c_s_axi_hp2_id_width=6
c_s_axi_hp2_data_width=64 c_s_axi_hp3_id_width=6 c_s_axi_hp3_data_width=64 c_m_axi_gp0_thread_id_width=12
c_m_axi_gp1_thread_id_width=12 c_num_f2p_intr_inputs=2 c_dq_width=32 c_dqs_width=4
c_dm_width=4 c_mio_primitive=54 c_ps7_si_rev=PRODUCTION c_fclk_clk0_buf=true
c_fclk_clk1_buf=false c_fclk_clk2_buf=false c_fclk_clk3_buf=false c_package_name=clg484
xlconcat/1
iptotal=1 x_ipproduct=Vivado 2013.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=xlconcat x_ipversion=1.0 x_ipcorerevision=-1 x_iplanguage=VHDL
num_ports=2 in0_width=1 in1_width=1 in2_width=1
in3_width=1 in4_width=1 in5_width=1 in6_width=1
in7_width=1 in8_width=1 in9_width=1 in10_width=1
in11_width=1 in12_width=1 in13_width=1 in14_width=1
in15_width=1 dout_width=2

report_utilization
slice_logic
slice_luts_used=3041 slice_luts_loced=0 slice_luts_available=53200 slice_luts_util_percentage=5.71
lut_as_logic_used=2979 lut_as_logic_loced=0 lut_as_logic_available=53200 lut_as_logic_util_percentage=5.59
lut_as_memory_used=62 lut_as_memory_loced=0 lut_as_memory_available=17400 lut_as_memory_util_percentage=0.35
lut_as_distributed_ram_used=0 lut_as_distributed_ram_loced=0 lut_as_shift_register_used=62 lut_as_shift_register_loced=0
slice_registers_used=1603 slice_registers_loced=1 slice_registers_available=106400 slice_registers_util_percentage=1.50
register_as_flip_flop_used=1603 register_as_flip_flop_loced=1 register_as_flip_flop_available=106400 register_as_flip_flop_util_percentage=1.50
register_as_latch_used=0 register_as_latch_loced=0 register_as_latch_available=106400 register_as_latch_util_percentage=0.00
f7_muxes_used=160 f7_muxes_loced=0 f7_muxes_available=26600 f7_muxes_util_percentage=0.60
f8_muxes_used=0 f8_muxes_loced=0 f8_muxes_available=13300 f8_muxes_util_percentage=0.00
slice_used=902 slice_loced=0 slice_available=13300 slice_util_percentage=6.78
lut_as_logic_used=2979 lut_as_logic_loced=0 lut_as_logic_available=53200 lut_as_logic_util_percentage=5.59
using_o5_output_only_used=0 using_o5_output_only_loced= using_o6_output_only_used=2574 using_o6_output_only_loced=
using_o5_and_o6_used=405 using_o5_and_o6_loced= lut_as_memory_used=62 lut_as_memory_loced=0
lut_as_memory_available=17400 lut_as_memory_util_percentage=0.35 lut_as_distributed_ram_used=0 lut_as_distributed_ram_loced=0
lut_as_shift_register_used=62 lut_as_shift_register_loced=0 using_o5_output_only_used=0 using_o5_output_only_loced=
using_o6_output_only_used=54 using_o6_output_only_loced= using_o5_and_o6_used=8 using_o5_and_o6_loced=
lut_flip_flop_pairs_used=3136 lut_flip_flop_pairs_loced=0 lut_flip_flop_pairs_available=53200 lut_flip_flop_pairs_util_percentage=5.89
fully_used_lut_ff_pairs_used=1436 fully_used_lut_ff_pairs_loced= lut_ff_pairs_with_unused_lut_used=95 lut_ff_pairs_with_unused_lut_loced=
lut_ff_pairs_with_unused_flip_flop_used=1605 lut_ff_pairs_with_unused_flip_flop_loced= unique_control_sets_used=27 minimum_number_of_registers_lost_to_control_set_restriction_used=45(Lost)
memory
block_ram_tile_used=0 block_ram_tile_loced=0 block_ram_tile_available=140 block_ram_tile_util_percentage=0.00
ramb36_fifo*_used=0 ramb36_fifo*_loced=0 ramb36_fifo*_available=140 ramb36_fifo*_util_percentage=0.00
ramb18_used=0 ramb18_loced=0 ramb18_available=280 ramb18_util_percentage=0.00
dsp
dsps_used=0 dsps_loced=0 dsps_available=220 dsps_util_percentage=0.00
io_and_gtx
bonded_iob_used=16 bonded_iob_loced=16 bonded_iob_available=200 bonded_iob_util_percentage=8.00
iob_master_pads_used=7 iob_master_pads_loced= iob_slave_pads_used=5 iob_slave_pads_loced=
bonded_ipads_used=0 bonded_ipads_loced=0 bonded_ipads_available=2 bonded_ipads_util_percentage=0.00
bonded_iopads_used=0 bonded_iopads_loced=0 bonded_iopads_available=130 bonded_iopads_util_percentage=0.00
ibufgds_used=0 ibufgds_loced=0 ibufgds_available=192 ibufgds_util_percentage=0.00
idelayctrl_used=0 idelayctrl_loced=0 idelayctrl_available=4 idelayctrl_util_percentage=0.00
in_fifo_used=0 in_fifo_loced=0 in_fifo_available=16 in_fifo_util_percentage=0.00
out_fifo_used=0 out_fifo_loced=0 out_fifo_available=16 out_fifo_util_percentage=0.00
phaser_ref_used=0 phaser_ref_loced=0 phaser_ref_available=4 phaser_ref_util_percentage=0.00
phy_control_used=0 phy_control_loced=0 phy_control_available=4 phy_control_util_percentage=0.00
phaser_out_phaser_out_phy_used=0 phaser_out_phaser_out_phy_loced=0 phaser_out_phaser_out_phy_available=16 phaser_out_phaser_out_phy_util_percentage=0.00
phaser_in_phaser_in_phy_used=0 phaser_in_phaser_in_phy_loced=0 phaser_in_phaser_in_phy_available=16 phaser_in_phaser_in_phy_util_percentage=0.00
idelaye2_idelaye2_finedelay_used=0 idelaye2_idelaye2_finedelay_loced=0 idelaye2_idelaye2_finedelay_available=200 idelaye2_idelaye2_finedelay_util_percentage=0.00
odelaye2_odelaye2_finedelay_used=0 odelaye2_odelaye2_finedelay_loced=0 odelaye2_odelaye2_finedelay_available=0 odelaye2_odelaye2_finedelay_util_percentage=0.00
ibufds_gte2_used=0 ibufds_gte2_loced=0 ibufds_gte2_available=0 ibufds_gte2_util_percentage=0.00
ilogic_used=0 ilogic_loced=0 ilogic_available=200 ilogic_util_percentage=0.00
ologic_used=0 ologic_loced=0 ologic_available=200 ologic_util_percentage=0.00
clocking
bufgctrl_used=1 bufgctrl_loced=0 bufgctrl_available=32 bufgctrl_util_percentage=3.12
bufio_used=0 bufio_loced=0 bufio_available=16 bufio_util_percentage=0.00
mmcme2_adv_used=0 mmcme2_adv_loced=0 mmcme2_adv_available=4 mmcme2_adv_util_percentage=0.00
plle2_adv_used=0 plle2_adv_loced=0 plle2_adv_available=4 plle2_adv_util_percentage=0.00
bufmrce_used=0 bufmrce_loced=0 bufmrce_available=8 bufmrce_util_percentage=0.00
bufhce_used=0 bufhce_loced=0 bufhce_available=72 bufhce_util_percentage=0.00
bufr_used=0 bufr_loced=0 bufr_available=16 bufr_util_percentage=0.00
specific_feature
bscane2_used=0 bscane2_loced=0 bscane2_available=4 bscane2_util_percentage=0.00
capturee2_used=0 capturee2_loced=0 capturee2_available=1 capturee2_util_percentage=0.00
dna_port_used=0 dna_port_loced=0 dna_port_available=1 dna_port_util_percentage=0.00
efuse_usr_used=0 efuse_usr_loced=0 efuse_usr_available=1 efuse_usr_util_percentage=0.00
frame_ecce2_used=0 frame_ecce2_loced=0 frame_ecce2_available=1 frame_ecce2_util_percentage=0.00
icape2_used=0 icape2_loced=0 icape2_available=2 icape2_util_percentage=0.00
startupe2_used=0 startupe2_loced=0 startupe2_available=1 startupe2_util_percentage=0.00
xadc_used=0 xadc_loced=0 xadc_available=1 xadc_util_percentage=0.00
primitives
fdre_used=1537 lut6_used=1238 lut5_used=1204 lut4_used=750
muxf7_used=160 lut3_used=134 bibuf_used=130 fdse_used=66
lut2_used=50 srlc32e_used=47 srl16e_used=23 carry4_used=12
obuf_used=8 lut1_used=8 ibuf_used=8 ps7_used=1
bufg_used=1

synthesis
command_line_options
-part=xc7z020clg484-1 -name=default::[not_specified] -top=design_wrapper -include_dirs=default::[not_specified]
-generic=default::[not_specified] -verilog_define=default::[not_specified] -constrset=default::[not_specified] -flatten_hierarchy=default::rebuilt
-gated_clock_conversion=default::off -directive=default::default -rtl=default::[not_specified] -bufg=default::12
-fanout_limit=default::10000 -shreg_min_size=default::3 -mode=default::default -fsm_extraction=default::auto
-keep_equivalent_registers=default::[not_specified] -resource_sharing=default::auto -control_set_opt_threshold=default::1
usage
elapsed=00:03:14s memory_peak=624.180MB memory_gain=473.301MB