Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
date_generatedWed Aug 7 14:33:46 2013 product_versionVivado v2013.2
build_version272601 os_platformLIN32
registration_id210701084_1777489062_0_015 tool_flowVivado
betaFALSE route_designTRUE
target_familyzynq target_devicexc7z020
target_packageclg484 target_speed-1
random_id076321c06bd65023ab135545b3942b69 project_id01fa6868d1eb4cd681ae33fad657821e
project_iteration3

user_environment
os_nameUbuntu os_releaseUbuntu 13.04
cpu_nameIntel(R) Core(TM) i5 CPU M 560 @ 2.67GHz cpu_speed2660.039 MHz
total_processors2 system_ram0.000 GB

vivado_usage
project_data
srcsetcount=9 constraintsetcount=0 designmode=RTL prproject=false
reconfigpartitioncount=0 reconfigmodulecount=0 hdproject=false partitioncount=0
synthesisstrategy=Vivado Synthesis Defaults implstrategy=Vivado Implementation Defaults currentsynthesisrun=synth_1 currentimplrun=impl_1
totalsynthesisruns=1 totalimplruns=1
other_data
guimode=8

unisim_transformation
pre_unisim_transformation
bufg=1 fdre=1090 gnd=4 ibuf=57
lut1=1 lut2=23 lut3=86 lut4=1166
lut5=90 lut6=372 muxf7=64 obuf=50
vcc=3
post_unisim_transformation
bufg=1 fdre=1090 gnd=4 ibuf=57
lut1=1 lut2=23 lut3=86 lut4=1166
lut5=90 lut6=372 muxf7=64 obuf=50
vcc=3

report_utilization
slice_logic
slice_luts_used=1668 slice_luts_loced=0 slice_luts_available=53200 slice_luts_util_percentage=3.13
lut_as_logic_used=1668 lut_as_logic_loced=0 lut_as_logic_available=53200 lut_as_logic_util_percentage=3.13
lut_as_memory_used=0 lut_as_memory_loced=0 lut_as_memory_available=17400 lut_as_memory_util_percentage=0.00
slice_registers_used=1090 slice_registers_loced=0 slice_registers_available=106400 slice_registers_util_percentage=1.02
register_as_flip_flop_used=1090 register_as_flip_flop_loced=0 register_as_flip_flop_available=106400 register_as_flip_flop_util_percentage=1.02
register_as_latch_used=0 register_as_latch_loced=0 register_as_latch_available=106400 register_as_latch_util_percentage=0.00
f7_muxes_used=64 f7_muxes_loced=0 f7_muxes_available=26600 f7_muxes_util_percentage=0.24
f8_muxes_used=0 f8_muxes_loced=0 f8_muxes_available=13300 f8_muxes_util_percentage=0.00
slice_used=530 slice_loced=0 slice_available=13300 slice_util_percentage=3.98
lut_as_logic_used=1668 lut_as_logic_loced=0 lut_as_logic_available=53200 lut_as_logic_util_percentage=3.13
using_o5_output_only_used=0 using_o5_output_only_loced= using_o6_output_only_used=1598 using_o6_output_only_loced=
using_o5_and_o6_used=70 using_o5_and_o6_loced= lut_as_memory_used=0 lut_as_memory_loced=0
lut_as_memory_available=17400 lut_as_memory_util_percentage=0.00 lut_as_distributed_ram_used=0 lut_as_distributed_ram_loced=0
lut_as_shift_register_used=0 lut_as_shift_register_loced=0 lut_flip_flop_pairs_used=1668 lut_flip_flop_pairs_loced=0
lut_flip_flop_pairs_available=53200 lut_flip_flop_pairs_util_percentage=3.13 fully_used_lut_ff_pairs_used=1089 fully_used_lut_ff_pairs_loced=
lut_ff_pairs_with_unused_lut_used=0 lut_ff_pairs_with_unused_lut_loced= lut_ff_pairs_with_unused_flip_flop_used=579 lut_ff_pairs_with_unused_flip_flop_loced=
unique_control_sets_used=3 minimum_number_of_registers_lost_to_control_set_restriction_used=6(Lost)
memory
block_ram_tile_used=0 block_ram_tile_loced=0 block_ram_tile_available=140 block_ram_tile_util_percentage=0.00
ramb36_fifo*_used=0 ramb36_fifo*_loced=0 ramb36_fifo*_available=140 ramb36_fifo*_util_percentage=0.00
ramb18_used=0 ramb18_loced=0 ramb18_available=280 ramb18_util_percentage=0.00
dsp
dsps_used=0 dsps_loced=0 dsps_available=220 dsps_util_percentage=0.00
io_and_gtx
bonded_iob_used=107 bonded_iob_loced=0 bonded_iob_available=200 bonded_iob_util_percentage=53.50
iob_master_pads_used=51 iob_master_pads_loced= iob_slave_pads_used=52 iob_slave_pads_loced=
bonded_ipads_used=0 bonded_ipads_loced=0 bonded_ipads_available=2 bonded_ipads_util_percentage=0.00
bonded_iopads_used=0 bonded_iopads_loced=0 bonded_iopads_available=130 bonded_iopads_util_percentage=0.00
ibufgds_used=0 ibufgds_loced=0 ibufgds_available=192 ibufgds_util_percentage=0.00
idelayctrl_used=0 idelayctrl_loced=0 idelayctrl_available=4 idelayctrl_util_percentage=0.00
in_fifo_used=0 in_fifo_loced=0 in_fifo_available=16 in_fifo_util_percentage=0.00
out_fifo_used=0 out_fifo_loced=0 out_fifo_available=16 out_fifo_util_percentage=0.00
phaser_ref_used=0 phaser_ref_loced=0 phaser_ref_available=4 phaser_ref_util_percentage=0.00
phy_control_used=0 phy_control_loced=0 phy_control_available=4 phy_control_util_percentage=0.00
phaser_out_phaser_out_phy_used=0 phaser_out_phaser_out_phy_loced=0 phaser_out_phaser_out_phy_available=16 phaser_out_phaser_out_phy_util_percentage=0.00
phaser_in_phaser_in_phy_used=0 phaser_in_phaser_in_phy_loced=0 phaser_in_phaser_in_phy_available=16 phaser_in_phaser_in_phy_util_percentage=0.00
idelaye2_idelaye2_finedelay_used=0 idelaye2_idelaye2_finedelay_loced=0 idelaye2_idelaye2_finedelay_available=200 idelaye2_idelaye2_finedelay_util_percentage=0.00
odelaye2_odelaye2_finedelay_used=0 odelaye2_odelaye2_finedelay_loced=0 odelaye2_odelaye2_finedelay_available=0 odelaye2_odelaye2_finedelay_util_percentage=0.00
ibufds_gte2_used=0 ibufds_gte2_loced=0 ibufds_gte2_available=0 ibufds_gte2_util_percentage=0.00
ilogic_used=0 ilogic_loced=0 ilogic_available=200 ilogic_util_percentage=0.00
ologic_used=0 ologic_loced=0 ologic_available=200 ologic_util_percentage=0.00
clocking
bufgctrl_used=1 bufgctrl_loced=0 bufgctrl_available=32 bufgctrl_util_percentage=3.12
bufio_used=0 bufio_loced=0 bufio_available=16 bufio_util_percentage=0.00
mmcme2_adv_used=0 mmcme2_adv_loced=0 mmcme2_adv_available=4 mmcme2_adv_util_percentage=0.00
plle2_adv_used=0 plle2_adv_loced=0 plle2_adv_available=4 plle2_adv_util_percentage=0.00
bufmrce_used=0 bufmrce_loced=0 bufmrce_available=8 bufmrce_util_percentage=0.00
bufhce_used=0 bufhce_loced=0 bufhce_available=72 bufhce_util_percentage=0.00
bufr_used=0 bufr_loced=0 bufr_available=16 bufr_util_percentage=0.00
specific_feature
bscane2_used=0 bscane2_loced=0 bscane2_available=4 bscane2_util_percentage=0.00
capturee2_used=0 capturee2_loced=0 capturee2_available=1 capturee2_util_percentage=0.00
dna_port_used=0 dna_port_loced=0 dna_port_available=1 dna_port_util_percentage=0.00
efuse_usr_used=0 efuse_usr_loced=0 efuse_usr_available=1 efuse_usr_util_percentage=0.00
frame_ecce2_used=0 frame_ecce2_loced=0 frame_ecce2_available=1 frame_ecce2_util_percentage=0.00
icape2_used=0 icape2_loced=0 icape2_available=2 icape2_util_percentage=0.00
startupe2_used=0 startupe2_loced=0 startupe2_available=1 startupe2_util_percentage=0.00
xadc_used=0 xadc_loced=0 xadc_available=1 xadc_util_percentage=0.00
primitives
lut4_used=1166 fdre_used=1090 lut6_used=372 lut5_used=90
lut3_used=86 muxf7_used=64 ibuf_used=57 obuf_used=50
lut2_used=23 lut1_used=1 bufg_used=1

synthesis
command_line_options
-part=xc7z020clg484-1 -name=default::[not_specified] -top=axi4_lite_register -include_dirs=default::[not_specified]
-generic=default::[not_specified] -verilog_define=default::[not_specified] -constrset=default::[not_specified] -flatten_hierarchy=default::rebuilt
-gated_clock_conversion=default::off -directive=default::default -rtl=default::[not_specified] -bufg=default::12
-fanout_limit=default::10000 -shreg_min_size=default::3 -mode=default::default -fsm_extraction=default::auto
-keep_equivalent_registers=default::[not_specified] -resource_sharing=default::auto -control_set_opt_threshold=default::1
usage
elapsed=00:00:42s memory_peak=392.184MB memory_gain=262.945MB

xsim
command_line_options
-sim_mode=behavioral -sim_type=default::