For machine vision applications we need to connect industrial cameras to the zedboard. These cameras often use Camera Link interfaces. Therefore we develop a FMC Module (LPC) with a Camera Link interface for the zedboard. Currently only the base configuration is supported. The second Camera Link connector on the board is a pusher for camera simulation and used for testing.
We tested the image data receiver successfully at clock rate of 85 MHz with the pusher output and with a AViiVA® SC2 CL Color linescan camera. The camera control signals work correctly, too.
The serial interface of Camera Link was only tested with a input output test. A timing test and the full integration into the operating system will follow in October.
Most of the development were done by students in there student research projects. Substantial contribution came from Nils Lindenthal (left) and Sascha Karmann (right).
Their documentations give detailed information about the hardware, firmware and software. The final work was done by Nils Lindenthal. Documentations are only available in German.
Karmann, S.: Link to document
Lindenthal, N.: Link to document
The layout was designed with CadSoft EAGLE PCB.
All source files can be downloaded from https://github.com/roy77/Cameralink-LPC-FMC-Module.
I developed a dynamic tester for VHDL beginners. This video gives an overview.
- Develop VHDL code and test it with a 32 In/Out Test interface
- Beginner environment for BCD2SevenSegment Decoder development
- Pattern generator with BCD code
- Seven-segment display output
- Beginner environment for Gray2Binary Decoder development
- Pattern generator with Gray code
The tester is based on GHDL and developed in C#.
Download tester with source code: VHDLSimulator
Start the program: VHDLSimulator\bin\Debug\VHDLSimulator.exe
Edit the VHDL soruce file: VHDLSimulator\bin\Debug\Inverter.vhdl
For simulation of VHDL Code the FPGA ventors Xilinx and Altera provide free „Web Editions“ of there products. The packets are very big and complex. GHDL is the only simple and open source VHDL simulator.
GHDL is a command line tool for simulation and generate a VCD (value change dump) file as result. gtkWave allow a visualization of the VCD file.
I set up a simple IDE based on Notepad++ for our students. The IDE allow VHDL code development and simulation without knowledge of GHDL or gtkWave.
The usage is simple. Open Notepad++Portable.exe in Notepad++Portable Folder. Select a project. Open a vhdl File an press F6 for simulation.
New projects and files can be added by pressing right mouse button on „Workspace“ treeview element. Important is to copy „run.bat“ to the new project.
A easier way is to copy and rename the folder of an existing project and running „setProjectFile.bat“ in Notepad++Portable Folder to update the workspace file. Restart Notepad++ or „Reload Workspace“ to update the Notepad++ view.
Download a the simulation system with two sample projects: VHDL_Simulation1